Ep 6: Quantum Computing Architectures with Dr. Fred Chong, University of Chicago

Dr. Partha Ranganathan is a VP and Technical Fellow at Google, where he serves as the area technical lead for hardware and datacenters. Partha is currently driving next-generation computing systems for the AI era, tackling the challenges of building, scaling and managing warehouse-scale computers, and the bleeding edge of hardware-software codesign. He has pioneered numerous impactful innovations touching billions of users--spanning power-efficient servers, specialized accelerators, and disaggregated datacenters. A leading voice in the field, Partha has published 100+ papers, is a co-inventor on 125+ patents, and co-authored the seminal textbook, "The Datacenter as a Computer." He is an IEEE and ACM Fellow, a member of the ISCA, ASPLOS, HPCA halls of fame, a recipient of the ACM SIGARCH Maurice Wilkes Award, MIT Tech Review's top-35 young innovators, distinguished alumni awards from Rice University and IIT Madras, and uniquely for a computer scientist, an Emmy Award.

Dr. Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Tech, who holds a Ph.D. from MIT. Tushar’s work shapes how the computing community designs modern large-scale distributed AI systems--spanning specialized accelerators, memory hierarchies, and communication fabrics--and driving design-space exploration with pioneering tools like ASTRA-sim, Chakra, and Garnet. A member of the ISCA, MICRO, and HPCA Halls of Fame, his impactful research has garnered over 21,000 citations and the 2025 DAC "Under 40 Innovators Award." He also actively shapes future AI computing standards as the Co-director of Georgia Tech's CRNCH and co-chair of the MLCommons Chakra Working Group.

Dr. Babak Falsafi is a Professor at EPFL, the founding president of the Swiss Data Center Efficiency Association, and the founder of EcoCloud, an academic consortium focused on sustainable IT. His contributions to computer architecture include the invention of spatial and temporal memory streaming (SMS prefetchers) found in ARM cores and laying the groundwork for fence speculation by defining memory ordering requirements in modern CPUs. He is a key figure in cloud-native server design, with his work forming the foundation for the first-generation Cavium ARM server CPUs. He is a former chair of the SIGARCH Executive Committee, a recipient of the Alfred P. Sloan Research Fellowship and a Fellow of both the ACM and IEEE.

Dr. Caroline Trippel is an Assistant Professor in the Computer Science and Electrical Engineering Departments at Stanford University. Caroline's research operates at the critical intersection of hardware and software, focusing on developing high-assurance computer architectures. Her work tackles the challenge of ensuring that complex hardware designs are correct and secure. She has pioneered automated tools that bridge the gap between a processor's implementation (its RTL) and its formal specification, as well as frameworks and compilers that find and mitigate hardware-related security vulnerabilities in software.

Dr. Ricardo Bianchini is a Technical Fellow and Corporate Vice President at Microsoft Azure, where he leads the team responsible for managing Azure’s compute workload, server capacity, and datacenter infrastructure with a strong focus on efficiency and sustainability. Before joining Azure, Ricardo led the Systems Research Group and the Cloud Efficiency team at Microsoft Research (MSR). He created research projects in power efficiency and intelligent resource management that resulted in large-scale production systems across Microsoft. Prior to Microsoft, he was a Professor at Rutgers University, where he conducted research in datacenter power and energy management, cluster-based systems, and other cloud-related topics. Ricardo is a Fellow of both the ACM and IEEE.