Ep. 019 - Inside the STEEL Lab: From Package to Transistor (Teardown Lab) | Afzal Ahmad, Andrew Wagner, Jordan Nanos
SemiAnalysis WeeklyShow Notes
SMIC's N+3 node shrank the M0 layer over 15% and cut SRAM area 10 to 20%, all without EUV. SemiAnalysis built a lab just for that; Andrew Wagner and Afzal Ahmad walk Jordan Nanos (@JordanNanos) through the STEEL teardown of Huawei's Kirin 9030, from package to transistor. They explain die shots, FIB and TEM cross sections, NPU discovery, cell height, and standard cell libraries. Then backside power, GAA, and where SMIC goes next. 00:00 Intro: The STEEL Teardown Lab01:02 What Is a Teardown?02:17 Who Uses Teardown Data03:22 SMIC N+3 and the Kirin 903005:02 Inside the Lab: Sourcing to Silicon09:10 Die Shots Explained12:35 The NPU Discovery15:42 Scaling Without EUV17:57 FIB, SEM, and TEM Cross Sections20:59 Cell Height and Transistor Shrink23:56 Standard Cell Libraries26:22 Export Bans and Huawei's Response27:40 What's Next: Backside Power and GAA32:43 Data Center GPUs and Logic Folding34:28 Closing Thoughts
Read More: https://newsletter.semianalysis.com/p/steel-smic-n3-teardown
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